1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to performance enhancement of semiconductor memory by using a self-time mechanism to selectively reduce a write interval and power consumption associated therewith.
2. Description of Related Art
Semiconductor memory is a crucial resource in modem computers, being used for data storage and program execution. With the exception of the central processor itself, no other component within the computer experiences as high a level of activity. Traditional trends in memory technology are toward greater density (more memory locations, or xe2x80x9ccells,xe2x80x9d per memory device), higher speed and improved efficiency. To some extent, these goals are inconsistent. For example, as memory speed increases, power consumption generally also rises.
There are various types of semiconductor memory, including Read Only Memory (ROM) and Random Access Memory (RAM). ROM is typically used where instructions or data must not be modified, while RAM is used to store instructions or data which must not only be read, but modified. ROM is a form of non-volatile storagexe2x80x94i.e., the information stored in ROM persists even after power is removed from the memory. On the other hand, RAM storage is generally volatile, and must remain powered-up in order to preserve its contents.
A conventional semiconductor memory device stores information digitally, in the form of bits (i.e., binary digits). The memory is typically organized as a matrix or array of memory cells, each of which is capable of storing one bit. The cells of the memory matrix are accessed by word lines and bit lines. Word lines are typically associated with the rows of the memory matrix, and bit lines with the columns. Raising a word line activates a given row; the bit lines are then used to read from or write to the corresponding cells in the currently active row. Memory cells are typically capable of assuming one of two voltage states (commonly described as xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d). Information is stored in the memory by setting each cell in the appropriate logic state. For example, to store a bit having the value 1 in a particular cell, one would select the cell by activating the appropriate bit line and word line and then set the state of that cell to xe2x80x9con;xe2x80x9d similarly, a 0 would be stored by setting the selected cell to the xe2x80x9coffxe2x80x9d state. Obviously, the association of xe2x80x9conxe2x80x9d with 1 and xe2x80x9coffxe2x80x9d with 0 is arbitrary, and could be reversed.
The two major types of semiconductor RAM, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), differ in the manner by which their cells represent the state of a bit. In an SRAM, each memory cell includes transistor-based circuitry that implements a bi-stable latch. A bi-stable latch relies on transistor gain and positive (i.e. reinforcing) feedback to guarantee that it can only assume one of two statesxe2x80x94xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d. The latch is stable in either state (hence, the term xe2x80x9cbi-stablexe2x80x9d). It can be induced to change from one state to the other only through the application of an external stimulus. Left undisturbed, it will remain in its original state indefinitely. This is just the sort of operation required for an SRAM memory circuit, since once a bit value has been written to the memory cell, it will be retained until it is deliberately changed. Each memory cell may be accessed using a pair of complementary bit lines. The bit lines are driven, to write a new value into the cell, or read by a sense amplifier, to read out the current value. Prior to each access, the bit lines must be pre-charged to a prescribed logic level.
The entire time interval required to complete a read or write operation to an SRAM memory cell is termed the read/write cycle time. The read cycle time has two components; a read access interval and a read pre-charge interval. During the read access interval, the logic state of the cell is acquired by the associated sense amplifier. The pre-charge interval immediately follows the read access. During the pre-charge interval, the bit lines associated with the cell are pre-charged to prepare for the next read cycle. Similarly, a write cycle consists of a write access interval (during which the input data is transferred into the memory cell), followed by a write pre-charge interval. For most SRAM memory devices, the read and write cycle times are not equal. The read access time is typically longer than the write access time, while the write pre-charge time is generally longer than the read pre-charge time.
In contrast to the SRAM, the memory cells of a DRAM employ a capacitor to store the xe2x80x9conxe2x80x9d/xe2x80x9coffxe2x80x9d voltage state representing the bit. A transistor-based buffer drives the capacitor. The buffer quickly charges or discharges the capacitor to change the state of the memory cell, and is then disconnected. The capacitor then temporarily holds the charge placed on it by the buffer and retains the stored voltage level.
DRAMs have at least two drawbacks compared to SRAMs. The first of these is that leakage currents within the semiconductor memory are unavoidable, and act to limit the length of time the memory cell capacitors can hold their charge. Consequently, DRAMs typically require a periodic refresh cycle to restore sagging capacitor voltage levels. Otherwise, the capacitive memory cells would not maintain their contents. Secondly, changing the state of a DRAM memory cell requires charging or discharging the cell capacitor. The time required to do this depends on the amount of current the transistor-based buffer can source or sink, but generally cannot be done as quickly as a bistable latch can change state. Therefore, DRAMs are typically slower than SRAMs. DRAMs offset these disadvantages by offering higher memory cell densities, since the capacitive memory cells are intrinsically smaller than the transistor-based latching cells of an SRAM.
SRAMs are widely used in applications where speed is of primary importance, such as the cache memory typically placed proximate to the processor or Central Processing Unit (CPU) in a personal computer. However, the timing of its internal circuitry may critically affect the speed and efficiency of the SRAM. For example, the bit line pre-charge interval comprises an appreciable portion of the read/write cycle time, and sense amplifier usage contributes significantly to the overall power consumption of the SRAM. In early SRAM memory designs, all read/write cycle timing was based on an externally generated clock signal. For example, if the SRAM were used in a microcomputer, the bus clock in the memory interface would determine the read/write timing characteristics of the SRAM.
Though conceptually simple, reliance on the bus clock results in excessive power consumption. One reason for this is that the sense amplifiers used to read the contents of each SRAM memory cell consume significant power while they are active. In the original approach described above, the sense amplifiers would remain active until the end of a memory cycle, as determined by the externally generated clock. In many cases, the sense amplifier would have completed its access of the respective cell before the end of the cycle, and would thus be maintained in an active state (consuming power) throughout a portion of the cycle when it was not serving any useful purpose.
To overcome the inefficiency of the above-described approach, SRAM manufacturers incorporated xe2x80x9cself-timexe2x80x9d circuitry into the internal SRAM circuitry, to control timing independently of the externally generated clock signal. The self-time circuitry establishes the interval allowed for reading or writing the contents of the memory locations, together with the subsequent pre-charge interval.
While this use of self-time circuitry improves efficiency, it is not an optimal solution. For simplicity, existing self-time schemes assign the same access and pre-charge times for both read and write memory accesses. Actually, this is a misrepresentation, since write access times are typically shorter than read access times, and write pre-charge times are generally longer than read pre-charge times. By forcing write cycle times to be longer than necessary, current self-time schemes may limit the speed of the SRAM and increase its power consumption.
It would be desirable to have a self-time circuit that applies different timing constraints for write accesses than for read accesses. Preferably, the improved self-time circuitry should be simple and easily adapted to conventional SRAM designs, and it use should not compromise the performance of the SRAM.
The use of self-time circuitry in memory devices can improve efficiency and speed, in comparison to straightforward schemes in which the timing of the memory""s internal circuitry is derived solely from an external clock. However, conventional self-time schemes assign the same pre-charge time interval and the same cell access interval for both read and write memory accesses. This typical approach has some drawbacks. Although pre-charge and access times differ for read and write operations, the longer of the two intervals is imposed by the self-time circuitry for both operations. Therefore, in at least some cases, the cycle time is longer than necessary, effectively reducing the speed of the memory. In addition, maintaining sense amplifiers and related circuitry in an active state longer than necessary may add significantly to the average power consumption of the memory.
Disclosed herein is a circuit and method for reducing the write cycle time and isolating it from the read cycle to reduce overall cycle time in a semiconductor memory, which overcomes the above problems. In an embodiment of the circuit disclosed herein, a xe2x80x9cdummyxe2x80x9d memory cell receives the same control signals used to write data to the functional cells of the memory. Unlike the other memory cells, the dummy cell cannot be externally accessed for the storage or retrieval of data. Although not an accessible storage location, the dummy cell is preferably structured identically to the accessible memory cells, so that it has exactly the same timing requirements. The dummy cell is configured to change its logic state at the beginning of the write operation, which coincides with data being transferred into any of the accessible memory cells. Upon completion of the write operation, the dummy cell issues a completion signal. A clock controller within the memory device, upon receiving the completion signal, terminates the write cycle and returns the dummy cell to its original state. Since the dummy cell is situated at the end of the signal path for the control signals, its state cannot toggle before the data transfer to the functional cells has completed. Therefore, the completion signal will not occur until after a write operation to any of the functional memory cells has concluded. When the write cycle is terminated, the clock controller also deactivates the clock signal to the memory device (to reduce power consumption), and initiates pre-charging of the bit lines (to prepare the memory cells for the next read/write operation).
The novel self-time circuit disclosed herein is adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM. In certain situations, read and write operations may take place simultaneously. This may occur, for example, with memory accesses performed by a microcontroller capable of independent input/output pin assignments. If applied in a memory device allowing simultaneous reads and writes, the present circuit may be used in conjunction with conventional self-time circuitry, which typically is based on the read access time. Simple logic can be employed to ensure that the cycle time for a concurrent read/write operation is the longer of the read access time and the write access time.
A method for reducing the write cycle time in a semiconductor memory is also disclosed herein. According to the method, data are transferred into functional memory cells at the start of the write interval, while a concurrent state change is induced in a dummy memory cell. Once the state change is latched in the dummy cell, a completion signal is issued. Upon detecting the completion signal, the write interval is terminated and the dummy write cell reset to its original logic state by a clock controller. Upon terminating the write interval, the clock controller may also deactivate the memory clock and initiate bit line pre-charging. The method also includes locating the dummy write cell at the end of the signal path used to write data into the functional cells, so that the state change in the dummy write cell does not occur until after the data transfer into the functional cells has completed.
Advantageously, the circuit disclosed herein allows write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This increases the overall operating speed of the memory device.